Temporal Partitioning for Partially-Reconfigurable-Field-Programmable Gate

The recent introduction of partially-reconfigurable-field-programmable gate arrays (PRFPGAs) has led to the need for new algorithms suited for use with these devices. Although algorithms developed for use with field-programmable gate arrays can be applied to PRFPGAs, these algorithms do not take advantage of features available in these new devices. This paper examines the applicability of PRFPGAs in hardware emulation systems. A partitioning algorithm known as temporal partitioning is introduced for use with PRFPGA-based hardware emulation systems. 1.0 Introduction Partitioning for field-programmable gate arrays (FPGAs) refers to the process of splitting a large circuit into smaller sub-circuits. The goal of partitioning is the creation of sub-circuits suitable for implementation in a single FPGA. These single FPGAs are interconnected in a way that allows the sub-circuits to communicate all necessary signals. The communicating sub-circuits are then known to implement the original circuit (which is assumed to not fit within a single FPGA). Although standard partitioning algorithms can be applied to interconnected partially-reconfigurable-field-programmable gate arrays (PRFPGAs), these algorithms do not exploit the partial reconfigurability of the target devices. In this paper, we introduce a partitioning technique known as temporal partitioning which allows a single PRFPGA to perform functions previously requiring an interconnected group of FPGAs. 2.0 Temporal Partitioning The minimum reconfiguration increment of PRFPGAs allows large circuits to be implemented by multiple reconfigurations of a single device. Accomplishing the same task with an FPGA requires an external memory coupled with on-chip control logic. Figure 1 shows an example circuit graph represented by large groups of interconnected gates. In this example, each edge is labeled with the number of signals communicated from node to node and each node is labeled with an identifier and number of contained gates. The total number of gates represented in this graph is 19,000. The target PRFGPA device for this example has a static capacity of 16,000 gates. While multiple groups may fit within the target PRFPGA, the entire circuit has a gate count larger than the static gate capacity of the device. With multiple reconfigurations, a single PRFPGA can implement this large circuit. Figure 2 shows one possible schedule for implementation of the example circuit.In this figure, one PRFPGA is assigned three different configurations: C0, C1, and C2. Communication between groups is handled by on-chip resources named signal storage points (SSPs). In the XC6200 series, SSPs can be implemented using available configurable logic block (CLB) registers. Groups, or partitions, of the circuit store their outputs in SSPs. The section of the device containing the SSPs is held while the section containing used circuitry is reconfigured. The newly configured circuit must be properly connected to the existing SSPs to provide the partition to partition interconnection. We refer to the process of clustering and then scheduling a design in this manner as temporal partitioning. The next sections detail our research into this new methodology. 2.1 Clustering Clustering is the first step in temporal partitioning. The objective of the clustering algorithm is to group nodes such that they may be subsequently scheduled. The cones partitioning algorithm provides the basis for our clustering stage. Clusters are formed as follows: * find external outputs * from each external output: recurse into the network and mark nodes with a corresponding label 5000